Field of the Invention
This invention relates to qualification and reliability characterization of integrated circuit (IC) fabrication processes, and more particularly to a programmable test structure for characterization of process variation and reliability of IC fabrication processes at the wafer, die or package levels.
Description of the Related Art
Increasing the performance of integrated circuits (ICs) requires a complete and accurate characterization of the variation and reliability of available IC fabrication processes. Established processes must be characterized to provide an IC designer with the information required to selected the appropriate process, specify tolerances of component devices, specify circuit performance, reliability and life time. Historically, IC fabrication processes have evolved to create new processes about every 18 months.
Process selection for a new IC product typically starts with an extensive study of initial process variation and device aging unique to that process. Device degradation will accumulate over time and with use and results in a continuous change in the electrical properties of transistors. Modern nanotechnology CMOS circuits have numerous reliability concerns that have to be accounted for during design and verification cycles. The circuits age during the operational life due to effects such as negative and positive bias temperature instabilities (NBTI, PBTI), time-dependent dielectric breakdown (TDDB), stress-induced leakage current (SILC), hot carrier injection (HCI) damage, electro-migration (EM), and stress migration (SM). The varying temperature extremes experienced by circuitry during operation also affects overall reliability and life time performance.
The process of characterizing any given IC fabrication process requires the fabrication of dedicated test devices in that target process. These devices are measurement circuits that are designed to measure device degradation. Electrical and thermal stress is applied to accelerate one or more failure modes. A program for accelerated life testing is then put into action so that the failure mechanisms can be recorded to generate a rate model for a bathtub curve. Failure mechanisms are accelerated by a number of means including the creation of a specific electrical stress bias and/or exposing the device to an extreme thermal environment. But transistors are 3 or 4 port devices and there is no single bias condition that activates all the different aging mechanisms simultaneously. Some failure mechanism are more relevant than others for a given application, so test devices are developed with specific dimensions and stress configurations to emphasis certain types of degradation. Thus, the characterization process is very much tailored to a specific IC fabrication process and product design objective.
In order to have accurate data to characterize process variation and lifetime, a statistically relevant number of devices, perhaps with multiple geometries, for multiple types of devices (e.g. pMOS and nMOS transistors and vias for a CMOS process) must be tested for multiple failure modes. Existing wafer, die and package-level systems subject test devices to a test either one device at a time or in parallel using expensive parallel probes and complex test systems. Package-level systems require multiple packaged test chips, each including a few test devices, in order to tests tens of the devices.